1. Field of the Invention
This invention relates to a semiconductor device having a trench for element isolation, for example, and a method for manufacturing the same, and more particularly to an NPN transistor having a trench formed for element isolation and a method for manufacturing the same.
2. Description of the Related Art
FIGS. 13A and 13B show the schematic structure of a conventional NPN transistor having a trench formed for element isolation. FIG. 13A is a cross sectional view showing the NPN transistor and FIG. 13B is a view schematically showing a mask pattern used for forming a field oxide film (insulating film for element isolation).
Next, the manufacturing process for the NPN transistor is explained by taking the NPN transistor shown in FIG. 13A as an example.
First, an N.sup.+ -type buried layer 102 and an N.sup.- -type epitaxial layer 103 are formed on an element, forming region of a P.sup.+ -type substrate 101. Then, an element isolation trench 105 is formed by forming a trench in an area adjacent to the element forming region and filling polysilicon 104 in the trench.
Next, a field oxide film 106 is formed by use of a mask (resist pattern) 120 as shown in FIG. 13B.
After the field oxide film 106 is formed, polysilicon is deposited on the structure and boron is ion-implanted into the polysilicon layer. Further, a silicon oxide film is deposited on the polysilicon layer, the silicon oxide film and polysilicon layer are etched to leave portions thereof which correspond to a base electrode so as to form a base polysilicon layer 107.
Next, the thermal diffusion process is effected to form an outer base region (P.sup.+) 108. Further, boron is ion-implanted with the base polysilicon layer 107 used as a mask to form an inner base region (P) 109.
Then, after a silicon oxide film is deposited, an anisotropic etching process is effected to form a side wall 110 on the inner wall of the base polysilicon layer 107.
After this, a protection film 111 is deposited and a portion of the protection film 111 which corresponds to an emitter electrode is removed by etching. Then, a polysilicon layer is deposited, arsenic is ion-implanted into the polysilicon layer and the polysilicon layer is etched to leave a portion thereof which corresponds to the emitter electrode so as to form an emitter polysilicon layer 112. Further, the thermal diffusion process is effected to form an emitter region (N.sup.+) 113.
Then, after a portion of the protection film 111 which corresponds to the collector electrode is etched, a deep N.sup.+ -type layer 114 used as a collector region is formed.
Next, a portion of the protection film 111 which corresponds to the base electrode is removed and wiring is performed by use of aluminum, for example, and the base electrode 115, emitter electrode 116 and collector electrode 117 are formed.
By effecting the above process, an NPN transistor in which the element isolation is made by use of the trench is constructed.
However, in the above conventional NPN transistor, since the field oxide film 106 formed on the trench 105 and the element isolation region extends into the element forming region, a distance (space) is provided from the boundary portion between the trench 105 and the element forming region adjacent to the trench 105 to the front end portion of the field oxide film 106. Therefore, the element area is increased by an amount corresponding to the space to increase the parasitic capacitance (Cjs), thereby causing the current consumption to be increased when the circuit is constructed.
Thus, in the prior art, since the front end portion of the field oxide film extends out the trench and extends into the element forming region, the element area is increased by an amount corresponding to the space between the trench and the front end portion of the field oxide film, that is, an extending amount of the field oxide film to increase the parasitic capacitance and increase the current consumption in the circuit.